The present invention relates generally to delay lines and more specifically to testing delay lines.
Delay lines are used in many applications in high speed circuitry. One such application is high speed memory interfaces. Specifically, delay lines are typically used in high speed memory (e.g., double data rate (DDR)) interfaces to adjust the timing of source-synchronous data and strobe signals with picosecond accuracy. Step sizes of delay lines (e.g., 90 nanometer delay lines) are typically 10-20 picoseconds and each delay line conventionally has, e.g., 128 delay steps.
There are delays associated with a processor communicating with a high speed (e.g., DDR) memory. For example, there are delays associated with communicating over a circuit board, delays associated with buffers and circuit board components, etc. As a result, there is an unpredictable delay between an external memory and the processor communicating with the external memory.
For synchronous communications between the processor and the external memory, a clock signal associated with the data communicated from the memory to the processor is shared between the two devices. As these communications occur at extremely high speeds, such as 400 or 800 Mbps, the placement of the edge of the clock signal becomes very important for sampling the data signal. Whatever data change is made (e.g., from a low value to a high value and then from the high value to the low value (or in the opposite direction)), the sampling clock signal (i.e., strobe) has to be centered about the data change to sample the bit correctly. One or more delay lines are used to adjust the delay of the data signal or the strobe in such a way that the clock signal is delayed by a quarter of the period (i.e., 90 degrees).
There are several types of delay lines, such as a slave delay, a minimum delay, and a master delay. A master delay receives a reference clock which has twice the frequency of the strobe and typically uses this reference clock to control one or more slave delay lines. The slave delay line has, e.g., 128 delay steps controlled by the master delay line. In 90 nm or smaller technology nodes, each step typically represents delay as low as 10-20 ps.
The master delay maintains its control over the slave delay during conditions of process, voltage, and temperature (PVT) associated with the processor. In particular, the master delay keeps the delay through the slave delay constant for all PVT.
In order to balance out the minimum attainable delay by the slave delay, a minimum delay cell can be used in other paths.
One problem with these delay lines is testing the delay lines. In particular, the time interval between the steps of a slave delay is typically 10-20 picoseconds and there are many steps. In a design, there may be hundreds of slave and minimum delay lines. Typical testing systems likely cannot accurately test the delay steps in a slave delay having such a miniscule time delay between steps and obtaining access to every delay line through the pins is not practical. Further, the delay associated with each delay step of a slave delay may be impacted by the process defects.
This delay error may lead to serious prior system problems in which the delay value needs to be controlled. A wrong delay step may inhibit the tuning of the system. To find the optimum sampling position in the presence of noise and jitter, delay lines have to be correct. When incorporated into a system, it often becomes extremely difficult to debug the problem as a faulty delay line.
Therefore, there remains a need to accurately test whether these delay lines are working properly.